The present invention relates to the field of data processing apparatus and in particular, to the field of conditional select instructions for selecting a source data element based on a condition.
Conditional instructions have been used in processing, for example by ARM® of Cambridge UK, and these instructions instruct a processor to perform processing operations only in response to predefined conditions being met. Examples of the conditions that may be required to be met are things such as less than, more than, equal to, negative, carry in, zero etc.
A disadvantage of these conditional instructions particularly in high end processing apparatus that perform instructions at least partially in parallel with each other, is that an instruction subsequent to the conditional instruction in the instruction stream that requires a result of the conditional instruction as in input, may require the original value or an updated result value depending on whether the condition is met or not. As the subsequent instruction may have entered the pipeline while the conditional instruction is still within the pipeline, either the original value or the result value may need to be made available in the pipeline to the subsequent instruction. This may require an additional read of the original value which has quite a high overhead in terms of speed and power.
Select instructions that cause a processor to select a result to be written to a destination register from a choice of two source registers based on a condition being met are also known.
It would be desirable to be able to keep much of the functionality of the conditional instructions while still maintaining performance.